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Concurrency – All the Way Down

18:00 - 19:00 Wednesday 11th March 2026 UTC
Advanced
Asynchronous

std::atomic and std::memory_order are utterly opaque abstractions. It feels like they were put in place to hide some monstrosity that is too complex for mortals to comprehend, and inevitably when trying to understand the underlying reality, the explanations end with 'the processor does weird things' and 'you can think about it as if...'.

Well, 'think about it as if' no more. In this talk we'll present the gory and wonderful mechanics of write buffers, invalidation queues, and some cache coherence protocols. We'll explain how modern hardware design makes different cores have different views of memory, and what the instructions for fence and read-modify-write do exactly - for both x86/64 and ARM/RISC-V. We'll also discuss the hardware implementation of fences and atomics.

This is an advanced low-level talk, placed at the borderline of software development and electrical engineering, on topics rarely surveyed at C++ conference talks.

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Ofek Shilon

Senior DeveloperSpeedata

A Mathematics MA by training, but a 25Y C++ developer, writer and speaker in both the Linux and MS universes. Compiler-explorer ('godbolt') maintainer, fascinated by compilers, debuggers and pretty much anything low level. Fiercely hated by his cat for no apparent reason.

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